Referenced Items are not available for this document.
In order to working together with ARP module in TCP/IP stack and making sure the high speed of ARP module, in this paper, with hardware language VHDL we re-code the cache portion of ARP protocol. According to the functional requirements of ARP cache by system, we re-code it in Xilinx ISE7.ll intergration environment, and in the meantime we did the simulation test in ModelSim. The simulation test results indicate that the re-designed ARP cache drops down a lot of cost both in space and time. The success of re-design of ARP cache with VHDL, will improve a lot of ARP working efficiency and as results to improve the whole system working speed of TCP/IP stack.
Published in:
Intelligent Information Hiding and Multimedia Signal Processing, 2007. IIHMSP 2007. Third International Conference on
(Volume:2
)
Date of Conference: 26-28 Nov. 2007
- Page(s):
- 373 - 376
- Print ISBN:
- 978-0-7695-2994-1
- INSPEC Accession Number:
- 9894275
- Conference Location :
- Kaohsiung
- Digital Object Identifier :
- 10.1109/IIHMSP.2007.4457727
- Product Type:
- Conference Publications
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