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Study of Dynamic Warpage of Flip Chip Packages under Temperature Reflow

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4 Author(s)
Chee Kan Lee ; Intel Technol. (Malaysia) Sdn. Bhd, Penang ; Wei Keat Loh ; Kang Eu Ong ; Chin, I.

Flip chip deforms after assembly due to coefficient of thermal expansion mismatch of silicon and substrate coupled with underfills. Issues arise when excessive package warpage leads to improper joint during surface mount technology and increase in assembly yield loss. In this paper, application of shadow moire technique and finite element modeling approach were introduced to study the thermo-mechanical response of various package types, material set and geometrical parameters example silicon die and substrate size. Finite element modeling results showed the package geometry has more influence on warpage with die and package size parameter for package without integrated heat spreader (I-HS).

Published in:

Electronics Manufacturing and Technology, 31st International Conference on

Date of Conference:

8-10 Nov. 2007

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