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Development of Novel Joint Resistance Modeling Technique for Flip Chip Interconnection Systems

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3 Author(s)
Yeo, A. ; Infineon Technol. Asia Pacific Pte Ltd., Singapore ; Wong Foo Lam ; Lee, C.

This paper presents the results of experimental work combined with analytical approach to explore the modeling methodology in joint resistance prediction. Single joint resistance of 1st level interconnects was evaluated by the 4-point Kelvin structure design in the flip chip ball grid array package. Various interconnect schemes such as solder (i.e. Cu pillar joint, SnAg solder joint and SnAgCu solder joint) and non-solder (i.e. AuStud-NCA joint and AuPlated-ACA joint) were investigated. Electro-thermal analysis was performed to predict the joint resistance. Different types of defects such as cracks and delamination in the flip chip interconnects on the joint resistance were investigated in the finite element analysis. Generally, solder interconnects show a lower joint resistance than non-solder interconnects, with Cu pillar joint having the lowest joint resistance. The analytical approach tends to under-estimate slightly the joint resistance, while the modeling method tends to over-predict but is in agreement with the measurement result in term of trend. A 50% reduction in the cross-sectional area of both the solder and non-solder interconnects did not show significant change in the joint resistance.

Published in:

Electronics Manufacturing and Technology, 31st International Conference on

Date of Conference:

8-10 Nov. 2007