By Topic

High-Work-Function Ir/HfLaO {\rm p} -MOSFETs Using Low-Temperature-Processed Shallow Junction

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

6 Author(s)
C. F. Cheng ; Nat. Chiao Tung Univ., Hsinchu ; C. H. Wu ; N. C. Su ; S. J. Wang
more authors

We report a high effective work function (Phim-eff) and a very low Vt Ir gate on HfLaO p-MOSFETs using novel self-aligned low-temperature shallow junctions. This gate-first process has shallow junctions of 9.6 or 20 nm that are formed by solid phase diffusion using SiO2-covered Ga or Ni/Ga. At 1.2-nm effective oxide thickness, good Phim-eff of 5.3 eV, low Vt of +0.05 V, high mobility of 90 cm2/V-s at -0.3 MV/cm, and small 85degC negative bias-temperature instability (NBTI) of 20 mV (10 MV/cm for 1 h) are measured for Ir/HfLaO p-MOSFETs.

Published in:

IEEE Transactions on Electron Devices  (Volume:55 ,  Issue: 3 )