Referenced Items are not available for this document.
Presented is an area-efficient architecture of a VLSI circuit that can perform various DCT-based transforms for a video decoder supporting multiple standards such as JPEG, MPEG-4, VC-1 and H.264. The proposed architecture uses a novel concept of a delta coefficient matrix and shares resources such as adders and shifters as much as possible. Multipliers are not included.
Published in:
Electronics Letters
(Volume:44
,
Issue:
4
)
Date of Publication: February 14 2008
- Page(s):
- 274 - 275
- ISSN :
- 0013-5194
- INSPEC Accession Number:
- 9943924
- Digital Object Identifier :
- 10.1049/el:20083168
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 25 February 2008
- Issue Date :
- February 14 2008
- Sponsored by :
- Institution of Engineering and Technology
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