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Fast-acquisition PLL using fully digital natural-frequency-switching technique

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5 Author(s)
M. Nakamura ; NTT Microsyst. Integration Labs., Atsugi ; A. Yamagishi ; M. Harada ; M. Nakamura
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A new phase-backed loop (PLL) with a simple architecture that overcomes the trade-off problem between acquisition time and phase noise was fabricated in a 0.2 mum CMOS process. One-fifth of the acquisition time of the integer-JV is achieved by switching only the division ratio with the optimised damping factor to control the natural frequency.

Published in:

Electronics Letters  (Volume:44 ,  Issue: 4 )