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Developers are actively pursuing embedments of the new HAIPE 3.1 standard for secure IP communications. Depending on underlying channel capacities or other aspects of individual applications, different levels of performance may be required. The challenge is to provide a hardware platform that provides the required level of computational support, but optimized with respect to cost, size, weight, etc. This paper will present an overview of these challenges and will describe an innovative, scalable hardware architecture that addresses them. Performance data was gathered for a series of architecture configuration experiments. Performance data is presented along with discussion and recommendations for future work.