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A New Architecture for High-Density High-Performance SGT nor Flash Memory

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6 Author(s)
Kadowaki, T. ; Res. Inst. Electr. Commun., Tohoku Univ., Sendai ; Yamakawa, Y. ; Nakamura, H. ; Kimura, Yasuo
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In order to overcome the limitation of a conventional NOR flash memory, we propose a new architecture using a surrounding gate transistor (SGT) NOR flash memory to realize both Fowler-Nordheim (FN)-tunneling program and high-speed random access read operation. The SGT NOR flash memory cell has a 3D structure, in which the source, gate and drain are vertically stacked. The gate surrounds a silicon pillar. The source line of a diffusion layer and the metal bit line (BL) are wired to the bottom and the top of the silicon pillar, respectively. The BL and SL are arranged in the same column direction and the gate line is wired in the row direction. This structure enables the same voltage to be simultaneously applied to both the SL and BL of the same column. Therefore, the SGT NOR flash memory cell can be written and erased by the FN-tunneling mechanism. In read operation, the metal common SL is connected with the SL every 16 memory cells to reduce the resistance of the SL. As a result, a read current is improved and a high-speed read operation can be achieved. Furthermore, the SGT NOR flash memory adapts to 50-nm node to obtain a compact cell area of 6.6 and a large read current of 72 muA; the cell area can be reduced by 54% and a read current increase by 227% compared to the conventional NOR flash memory. Owing to high-density and high-speed features, the SGT NOR flash memory is a promising structure for the future high-density and high-performance flash memory.

Published in:

Circuits and Systems II: Express Briefs, IEEE Transactions on  (Volume:55 ,  Issue: 6 )

Date of Publication:

June 2008

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