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Binary-decision diagrams (BDDs) have proven to be an efficient means to represent and manipulate Boolean formulas and sets due to their compactness and canonicity. In this paper, we leverage the efficiency of BDDs for new areas in field-programmable gate-array (FPGA) computer-aided design (CAD) flow including cut generation and clustering by reducing these problems to BDDs and solving them using Boolean operations. As a result, we show that this leads to more than 10 reduction in runtime and memory use when compared to previous techniques, as reported by Mishchenko and Lin. This speedup allows us to apply this paper to new areas in the FPGA CAD flow previously not possible. Specifically, we introduce a new method to solve the logic-synthesis elimination problem found in FBDD, a reported BDD synthesis engine with an order-of-magnitude speedup over SIS. Our new elimination algorithm results in an overall speedup of 6 in FBDD with no impact on circuit area.