By Topic

Fast Design Space Exploration Using Local Regression Modeling With Application to ASIPs

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Hallschmid, P. ; British Columbia Univ., Vancouver ; Saleh, R.

The configuration of an application-specific instruction-set processor through an exhaustive search of the design space is computationally prohibitive. Consequently, we propose a novel algorithm that models the design space using local regression statistics. With only a small subset of the design space sampled, our model uses statistical inference to estimate all remaining points. This technique enables existing design space exploration approaches to make longer strides toward the optimal point while evaluating fewer points in the design space. We tested our approach on two important aspects of processor architecture. Initially, we optimized the pattern history table (PHT) of a GSelect branch predictor to minimize the total energy of an embedded processor. Our approach was able to find the optimal configuration for the majority of benchmarks tested. By configuring the PHT size using our approach, the total processor energy was reduced by 17.2% on average, which is close to the possible percentage of 17.6% using optimal configurations. We then extended our approach to a multidimensional cache tuning problem where we configured a two-level cache hierarchy with 19 278 possible configurations. In this case, only 1% of the design space was simulated, resulting in a 100 times speedup. In doing so, we were able to identify near optimal configurations for most benchmarks and reduce the overall energy of the processor by 13.9% on average, with one benchmark by as much as 53%.

Published in:

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:27 ,  Issue: 3 )