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Joint Equalization and Coding for On-Chip Bus Communication

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3 Author(s)
Sridhara, S.R. ; Texas Instrum., Dallas ; Balamurugan, G. ; Shanbhag, N.R.

In this paper, we propose using joint equalization and coding to improve on-chip communication speeds by signaling at rates beyond the rate governed by resistance-capacitance (RC) delay of the interconnect. Operating beyond the RC limit introduces inter-symbol interference (ISI). We mitigate the effects of ISI by employing equalization. The proposed equalizer employs a variable threshold inverter whose switching threshold is modified as a function of past output of the bus. We demonstrate even higher speedups by combining equalization with crosstalk avoidance coding. Specifically, simulation results for a 10-mm 32-bit bus in 0.13-mum CMOS technology show that 1.28 speedup is achievable by equalization alone and 2.30 speedup is achievable by joint equalization and coding.

Published in:

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:16 ,  Issue: 3 )

Date of Publication:

March 2008

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