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Very fast chip-level thermal analysis

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3 Author(s)
Nakabayashi, K. ; Nara Inst. of Sci. & Technol., Nara ; Nakabayashi, T. ; Nakajima, K.

We present a new technique of VLSI chip-level thermal analysis. We extend a newly developed method of solving two dimensional Laplace equations to thermal analysis of four adjacent materials on a mother board. We implement our technique in C and compare its performance to that of a commercial CAD tool. Our experimental results show that our program runs 5.8 and 8.9 times faster while keeping smaller residuals by 5 and 1 order of magnitude, respectively.

Published in:

Thermal Investigation of ICs and Systems, 2007. THERMINIC 2007. 13th International Workshop on

Date of Conference:

17-19 Sept. 2007