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Highly vectorizable fault simulation on the Cray X-MP supercomputer

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2 Author(s)
Daoud, R. ; Dept. of Electr. Eng., Ohio State Univ., Columbus, OH, USA ; Ozguner, F.

A highly vectorizable parallel fault simulation algorithm for high-speed fault simulation of combinational circuits, developed to take advantage of the specific hardware architecture of the Cray X-MP vector supercomputer, is described. The algorithm takes into account the memory organization of the supercomputer, reduces the number of vector fetches per gate simulation, and overlaps computation and I/O. Experimental results on large benchmark circuits show that very high evaluation rates (3.0-3.5×109 evaluations/s) comparable to those of hardware logic simulation energies can be achieved. Speedup factors of 50-60 observed between scalar and vector execution of the simulator on the Cray X-MP/28 are reported

Published in:

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:8 ,  Issue: 12 )

Date of Publication:

Dec 1989

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