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Implementation and Evaluation of Parallel FFT Using SIMD Instructions on Multi-core Processors

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1 Author(s)
Takahashi, D. ; Univ. of Tsukuba, Tsukuba

In this paper, an implementation of a parallel two- dimensional fast Fourier transform (FFT) using short vector SIMD instructions on multi-core processors is proposed. Combination of vectorization and the block two- dimensional FFT algorithm is shown to effectively improve performance. We vectorized FFT kernels using Intel's streaming SIMD extensions 3 (SSE3) instruction. The performance results for two-dimensional FFTs on multi-core processors are reported. We succeeded in obtaining a performance of over 2.7 GFLOPS on a dual-core Intel Xeon (2.8 GHz, two CPUs, four cores) and over 3.3 GFLOPS on an Intel Core2 Duo E6600 (2.4 GHz, one CPU, two cores) for a 210 times 210 -point FFT.

Published in:

Innovative architecture for future generation high-performance processors and systems, 2007. iwia 2007. international workshop on

Date of Conference:

11-13 Jan. 2007