By Topic

Power Attack Resistant Efficient FPGA Architecture for Karatsuba Multiplier

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Rebeiro, C. ; Indian Inst. of Technol., Chennai ; Mukhopadhyay, D.

The paper presents an architecture to implement Karatsuba Multiplier on an FPGA platform. Detailed analysis has been carried out on how existing algorithms utilize FPGA resources. Based on the observations the work develops a hybrid technique which has a better area delay product compared to the known algorithms. The results have been practically demonstrated through a large number of experiments. Subsequently, the work develops a masking strategy to prevent power based side channel attacks on the multiplier. It has been found that the proposed masked Hybrid Karatsuba multiplier is more compact compared to existing designs.

Published in:

VLSI Design, 2008. VLSID 2008. 21st International Conference on

Date of Conference:

4-8 Jan. 2008