Cart (Loading....) | Create Account
Close category search window

A Robust Top-Down Dynamic Power Estimation Methodology for Delay Constrained Register Transfer Level Sequential Circuits

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Sambamurthy, S. ; Univ. of Texas at Austin, Austin ; Abraham, J.A. ; Tupuri, R.S.

We present a top-down dynamic power estimation methodology for delay constrained sequential circuits. The methodology works at the register transfer level (RT-Level), and applies to both structural and behavioral descriptions of circuits. The average power consumption of a circuit varies with the worst case cycle-time or frequency of operation. As the cycle-time is reduced, the increase in the capacitance of the circuit due to technology mapping and optimization is captured by our technique at the RT-Level using the principles of logical effort. Switching activity is obtained at the RT-Level visible nodes through RT-Level functional simulation. This information is utilized to approximate the activities at the remaining nodes of the circuit and combined with capacitance to estimate dynamic power. Power estimation results for RT-Level sequential circuits indicate good accuracy (average error<10%) with respect to the reference values obtained by detailed gate-level power analysis. The power consumed by a circuit varies with the target library and technology. Our methodology is parameterizable and the results obtained for different target libraries at 0.18 mum TSMC and 0.13 mum UMC technologies are consistent, indicating the robustness of our technique. The applicability of our methodology in design frameworks consisting of bottom-up techniques is also discussed.

Published in:

VLSI Design, 2008. VLSID 2008. 21st International Conference on

Date of Conference:

4-8 Jan. 2008

Need Help?

IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.