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Adders and multipliers are the most important arithmetic units in a general microprocessor and the major source of power dissipation. Various architecture styles exist to implement these units, each having their own merits and demerits. However, due to continuing integrating intensity and growing needs of portable devices, low power design is of prime importance. In addition, much power is dissipated due to a large number of spurious transitions on internal nodes in power hungry multiplier structures. We present a new full adder structure based on complementary pass transistor logic (CPL) which is faster and more energy efficient than the existing structures. We also propose a new technique of implementing multiplier circuit using decomposition logic which improves speed and reduces power consumption by reducing the spurious transitions on internal nodes. Combined with the new adder structure and the decomposition logic, there is substantial improvement in the performance of the multiplier structures. With the help of these state of the art designs, it would be possible to design highly power efficient processors, especially digital signal processors. We have used TSPICE for simulation in the TSMC 180 nm technology.
Date of Conference: 4-8 Jan. 2008