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A Modeling of a Dynamically Reconfigurable Processor Using SystemC

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3 Author(s)
Kitamichi, J. ; Univ. of Aizu, Aizu-Wakamatsu ; Ueda, K. ; Kuroda, K.

Recently, dynamically reconfigurable processors (DRPs) have been proposed. In this paper, we describe a model of a DRP using a dynamic module library (DML), which we have developed for the modeling of general-purpose dynamically reconfigurable systems. The DML is an extended SystemC library and enables the modeling of the dynamic generation and elimination of modules, ports and channels and the dynamic connection and dispatch between port and channel. Using the DML, we can model the DRP naturally. The architecture of the proposed DRP is based on an MlPS-type architecture and supports the instructions, which are for the dynamically reconfigurable operational units and for their generation and elimination. We describe the proposed DRP model and its evaluation results.

Published in:

VLSI Design, 2008. VLSID 2008. 21st International Conference on

Date of Conference:

4-8 Jan. 2008