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As designs scale further into the nanometer regime, the vulnerability of logic circuits in commodity products to soft errors is increasing and their contribution towards total chip soft-error rate (SER) is predicted to be as high as 60%, much more than that of memory. We employ a value-aware framework that enables operation bypass in combinational circuits to simultaneously reduce both energy consumption and SER in them. Unlike techniques that reduce SER in combinational logic with very high performance and/or energy overheads (since they usually employ significant explicit spatial or temporal redundancy), our technique dynamically exploits operand values by shutting off portions of combinational circuits, thus reducing vulnerable area and energy consumption with minimal performance overheads. On the average across the SPEC CPU2k benchmark suite, we obtain 60% SER reduction and 24% energy savings with minimal impact on performance.
Date of Conference: 4-8 Jan. 2008