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This tutorial will provide a bottom-up view of the changes in semiconductor memory design as we move into the nanometer regime. We begin by discussing the breakdown of scaling and the power problem. As innovation replaces classical scaling we investigate the use of stress engineering to improve device level performance. Technology challenges in lithography and interconnects are addressed. The consequences of innovation and scaling on RF/Analog characteristics must also be considered. The scaling of memory presents yet another challenge. We proceed to discuss the modeling of these effects for the circuit designer including discussion of the many new and traditional sources of variation. We describe how these are characterized how they can be controlled by layout rules and how the remaining variation can be describe in the model to enable Statistical Timing and other advanced circuit techniques. At the circuit level we consider in detail embedded DRAM and SRAM design for both bulk and SOI. We discuss the benefits and challenges of advanced technologies including methods for creating robust designs in the presence of manufacturing variation. We also discuss the design innovations required to utilize advanced technologies for overcoming the "memory wall", "power wall" and "ILP wall".
Date of Conference: 4-8 Jan. 2008