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A 12 Bit Direct Level-Signal Transition Based Pipelined Analog-to-Digital Converter

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2 Author(s)
Hsu, T.Y. ; Nat. Changhua Univ. of Educ., Changhua ; Lin, Z.M.

This paper presents a 12-bit 100-MS/s pipelined analog-to-digital converter designed in a 0.18-mum CMOS process. Unlike conventional pipelined analog-to-digital converters, we use a direct level-signal transition technique to replace the traditional digital-to-analog converter. The designed ADC consumes 43 mW power from a 1.8 V power supply. Simulated static DNL and INL errors are 0.5 LSB and 0.73 LSB, respectively. Compared with the traditional ADCs, our method can reduce up to 80% of transistor numbers.

Published in:

Electron Devices and Solid-State Circuits, 2007. EDSSC 2007. IEEE Conference on

Date of Conference:

20-22 Dec. 2007