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A Power Aware Design Technique for High Performance Self-Timed Datapaths

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2 Author(s)

The aim of this research attempts to explore a power aware design technique for high-speed self-timed datapaths using DCVSL circuits. The study involved a survey, comprised of three completion detection techniques and two well-known self-timed implementations using dynamic logics. Then we reveal a self-timed datapath design technique that encloses the functional block within the proposed self-timed wrapper that communicates using four-phase handshaking. Experimental results of this study showed an average about 20% less power when the single-level functional blocks are implemented using our wrapper. Approximately 35% power reduction is obtained when a multi-level functional block, a 4-stage carry chain, is realized. Obviously, the findings indicate that the proposed self-timed wrapper is not merely excellent for small-size self-timed module creation but even better for more realistic self-timed datapaths development.

Published in:

Electron Devices and Solid-State Circuits, 2007. EDSSC 2007. IEEE Conference on

Date of Conference:

20-22 Dec. 2007

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