Scheduled System Maintenance:
On May 6th, single article purchases and IEEE account management will be unavailable from 8:00 AM - 12:00 PM ET (12:00 - 16:00 UTC). We apologize for the inconvenience.
By Topic

A Low Offset High Voltage Swing Rail-to-Rail Buffer Amplifier for LCD Driver

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Guo-Teng Hong ; Nat. Changhua Univ. of Educ., Changhua ; Chih-Hsiung Shen

The size of LCDs is getting larger in particular , it is essential to compromise the driving ability. So , source drivers with high performance, high resolution, and low power dissipation will achieve more additional value. This paper presents a design and implementation of using 10-bit multiple DAC (digital to analog converter) for the driver , and proposes a rail-to-rail output buffer with low offset and high driving ability. We designed a class-B output buffer with offset compensation ability to reduce the nonlinearity of output voltage. With the H-SPICE model of TSMC 0.35 mum 2P4M 3.3 V / 5 V process, the maximum offset is less than 2 mV , and the input / output swing are nearly full swing. Besides , it also performs a rail-to-rail swing range and high slew rate of 14 V / mus and 11.5 V /mus for rising and falling edges under a 400 pF capacitance load. For high driving capability , two push-pull output stages are used , two frequency compensation stages are also introduced for stability , one is the miller compensation with 0.04 pF capacitance , and the other is zero compensation with 0.1 kOmega added between two push-pull output stages for stable driving under different capacitance loads. The result exhibits that the settling time are within 5 mus under the max voltage swing with voltage 5 V under a 400 pF capacitance load. Even under a 1000 pF capacitance load , it still has the settling time of 1.52 mus and 1.80 mus for rising and falling edges , respectively. The effective area of this buffer is only 100 x 100 mum2 with build-in offset voltage holding capacitor.

Published in:

Electron Devices and Solid-State Circuits, 2007. EDSSC 2007. IEEE Conference on

Date of Conference:

20-22 Dec. 2007