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A voltage multiplier for passive RFID tags is designed in a 0.35-μm 2-poly 4-metal CMOS technology. Due to the limitations of the technology, an optimized design is difficult to achieve easily. Based on some design studies, an voltage multiplier working at 13.5 MHz is developed and realized on silicon. From the measurement, the output voltage is about 2.5 V and the output current is 6.4 μA. when an input AC signal of 1.5 Vpp is applied. Circuit simulation shows that the power efficiency can be 16.25% in the optimized case.
Date of Conference: 20-22 Dec. 2007