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Design challenges of voltage multiplier in a 0.35-μm 2-poly 4-metal CMOS technology for RFID passive tags

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6 Author(s)
Hiu Yeung Lo ; Chinese Univ. of Hong Kong, Shatin ; Pui Ying Or ; Ka Nang Leung ; Lai Kan Leung
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A voltage multiplier for passive RFID tags is designed in a 0.35-μm 2-poly 4-metal CMOS technology. Due to the limitations of the technology, an optimized design is difficult to achieve easily. Based on some design studies, an voltage multiplier working at 13.5 MHz is developed and realized on silicon. From the measurement, the output voltage is about 2.5 V and the output current is 6.4 μA. when an input AC signal of 1.5 Vpp is applied. Circuit simulation shows that the power efficiency can be 16.25% in the optimized case.

Published in:

Electron Devices and Solid-State Circuits, 2007. EDSSC 2007. IEEE Conference on

Date of Conference:

20-22 Dec. 2007