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A New Low Power Flash ADC Using Multiple-Selection Method

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4 Author(s)
Wen-Ta Lee ; Nat. Taipei Univ. of Technol., Taipei ; Po-Hsiang Huang ; Yi-Zhen Liao ; Yuh-Shyan Hwang

This paper presents new low power CMOS flash analog-to-digital converter (ADC) using multiple-selection method. As an example of 6-bit flash ADC, we use three extra comparators in our design to divide the next stage into four sections and control the switches whether can proceed to the 4-bit modified flash ADC or not. We use multiple-selection method to let only one section of the 4-bit modified flash ADC is allowed to operate, which achieve the aim of the low power consumption. Simulation and experimental results show that this proposed 6-bit flash ADC consumes about 19.2 mW at 800 M sample/s with 3.3 V supply voltage in TSMC 0.35 mum 2P4M process. Compared with the traditional flash ADC, this multiple-selection method can reduce about 80.3% in power consumption.

Published in:

Electron Devices and Solid-State Circuits, 2007. EDSSC 2007. IEEE Conference on

Date of Conference:

20-22 Dec. 2007