Referenced Items are not available for this document.
A physically based, quantum mechanical model is presented for C-V characteristics of MOS devices with ultrathin high-K gate dielectrics including interface trap and wave function penetration effects. Numerical results show that C-V curves are rather sensitive to the details of the interface trap distributions. The proposed model may be used for accurately extracting profiles of interface trap states from low frequency C-V measurement.
Published in:
Electron Devices and Solid-State Circuits, 2007. EDSSC 2007. IEEE Conference on
Date of Conference: 20-22 Dec. 2007
- Page(s):
- 157 - 159
- E-ISBN :
- 978-1-4244-0637-1
- Print ISBN:
- 978-1-4244-0637-1
- INSPEC Accession Number:
- 9856142
- Conference Location :
- Tainan
- Digital Object Identifier :
- 10.1109/EDSSC.2007.4450086
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