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Modeling Effects of Interface Trap States on the Gate C-V Characteristics of MOS Devices with Ultrathin High-K Gate Dielectrics

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2 Author(s)
Md. M. Satter ; Department of Electrical and Electronic Engineering, Bangladesh University of Engineering and Technology, Dhaka-1000, Bangladesh. Email: ; A. Haque

A physically based, quantum mechanical model is presented for C-V characteristics of MOS devices with ultrathin high-K gate dielectrics including interface trap and wave function penetration effects. Numerical results show that C-V curves are rather sensitive to the details of the interface trap distributions. The proposed model may be used for accurately extracting profiles of interface trap states from low frequency C-V measurement.

Published in:

Electron Devices and Solid-State Circuits, 2007. EDSSC 2007. IEEE Conference on

Date of Conference:

20-22 Dec. 2007