Modeling Effects of Interface Trap States on the Gate C-V Characteristics of MOS Devices with Ultrathin High-K Gate Dielectrics

A physically based, quantum mechanical model is presented for C-V characteristics of MOS devices with ultrathin high-K gate dielectrics including interface trap and wave function penetration effects. Numerical results show that C-V curves are rather sensitive to the details of the interface trap distributions. The proposed model may be used for accurately extracting profiles of interface trap states from low frequency C-V measurement.