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In this paper we present a Digital Phase Locked Loop (D-PLL), based on an arctan phase detector for complex signals, implemented on a Field Programmable Gate Array (FPGA) together with its performance analysis. The work is motivated by the requirement of signal synchronisation in Software Defined Radios (SDR) for high speed communication receivers. The theoretical model for the D-PLL and its corresponding implementation methodology on a Xillinx Virtex- IV FPGA are given in this paper. We also provide some test results and simulations results on the implemented system and verify them using the theoretical models.