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It presents a novel digit-serial architecture for finite field multiplications over GF(2m) defined by irreducible trinomials as field polynomials. The critical path of the proposed structure is reduced, and a saving of m number of XOR gates is achieved by the proposed structure at the final output stage by successive finite field accumulation through T flip-flops instead of using D flip-flops and XOR gates in sequential loop. The proposed design is highly modular, and consists of regular blocks of AND and XOR logic gates. The details of hardware requirement and computational delay of the proposed multiplier have been estimated and compared with those of the existing designs. It is found that the proposed design offers considerably lower area-time complexity compared with the existing designs. The advantage of the proposed design is mainly based on its lower critical path, optimal logic design and 100% hardware utilization efficiency.