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Fully integrated active filter design forultra low frequency application

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3 Author(s)
Darweesh, H.Y. ; Zagazig Univ., Zagazig ; Khalaf, Y.A. ; Farag, F.A.

This paper presents a new active capacitance multiplier circuit, by which it is possible to obtain higher capacitance values. The capacitance multiplier is based on cascaded current multiplier cells (CMC). The proposed circuit is preferred for low power low voltage applications since it is based on CMOS inverters and op-amps. The capacitance multiplier is employed in the design of a first order LPF with a cutoff frequency as low as 135 Hz using an on-chip capacitor of 1 pF only. The circuit is simulated in CMOS 0.13 mum process. Simulation results show close agreement with the analytical calculations.

Published in:

Design & Technology of Integrated Systems in Nanoscale Era, 2007. DTIS. International Conference on

Date of Conference:

2-5 Sept. 2007

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