Cart (Loading....) | Create Account
Close category search window
 

Generalized Circuit Techniques for Low-Voltage High-Speed Reset- and Switched-Opamps

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Sai-Weng Sin ; Analog & Mixed-Signal VLSI Lab., Univ. of Macau, Macao ; Seng-Pan U ; Martins, R.P.

This paper presents several comprehensive and novel circuit techniques that can be efficiently applied to low-voltage (LV) high-speed reset-opamp (RO) and switched-opamp (SO) in LV switched-capacitor circuits. The first, designated as virtual-ground common-mode (CM) feedback with output CM error correction, allows the design of fully differential RO circuits that could only be traditionally implemented before in pseudo-differential mode, and it leads to considerable savings of half of the opamps' power. The second, uses a crossed-coupled passive sampling interface to avoid the extra track-and-reset stages as required in both RO and SO circuits, further saving one front-end opamp's power. The third, employs a voltage-controlled level-shifting (LS) technique that utilizes the charge redistribution property to process the CM LS in an LV environment, avoiding the degradation of the feedback factor by the use of extra LS circuits. Finally, the fourth, the LV finite-gain compensation technique allows the use of low-gain high-speed single-stage amplifier in contrast to the conventional high-gain, low-speed two-stage opamp to achieve a high-speed operation in both RO and SO circuits. Without any clock boosting or bootstrap circuits, all of the above techniques can be applied in LV applications without any floating switches limitations. Measurement results of a 1.2-V 10-bit 60 MS/s pipelined analog-digital converter in 0.18- mum CMOS with RO are presented to verify the effectiveness of the proposed techniques, achieving a signal-to-noise distortion ratio of 55.2 dB with 85-mW power consumption.

Published in:

Circuits and Systems I: Regular Papers, IEEE Transactions on  (Volume:55 ,  Issue: 8 )

Date of Publication:

Sept. 2008

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.