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The authors of this article illustrate a means to use design models and simulation testbenches to decrease manufacturing test costs. This technique enables test cost optimization early in the RFIC design phase. In this article, we propose a test set optimization and qualification method that targets test application time, cost, and quality while also decreasing the generation time of production tests. Our approach decreases the manufacturing test cost of AMS and RF SoCs by automatically qualifying and optimizing existing test sets. We present a computer-aided test (CAT) tool, Plasma (platform for system qualification with mixed and analog signals), that uses fault injection and a fault simulation technique to perform test qualification and generation. This tool reduces both test time and test equipment cost using a high-level fault model. Our approach relies on the qualification and optimization of a predefined test set. With this article, we show how to reduce the test optimization time by using behavioral modeling and decreasing the number of simulated circuits. This method reduces the number of simulated fault-free models, thanks to a normal estimation.