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Implementing high speed communication buses for a FPGA-DSP architecture for digital control of power electronics

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4 Author(s)
Girón, C. ; Alcala Univ., Alcala de Henares ; Rodriguez, F.J. ; Huerta, F. ; Bueno, E.

This paper describes a communication architecture for a digital controller based on DSP-FPGA to be used in power electronic systems. For high rate transmissions, the proposed architecture has an USB bus implemented with a minimum use of the DSP core, using enhanced direct memory access and external memory interface modules of a TMS320C6713 high performance DSP and Cypress EZ-USB SX2trade high-speed USB interface device. Moreover, this architecture has CAN-bus communications to expand system with others subsystem, and a compact flash interface to storage data and DSP program, improving platform to boot alone. Host side has an application interface programmed in C with multithreading to process all data due high speed transfers.

Published in:
Intelligent Signal Processing, 2007. WISP 2007. IEEE International Symposium on

Date of Conference: 3-5 Oct. 2007

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