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The use of the multipartite table methods (MTMs) to implement high-performance direct digital frequency synthesizers (DDFSs) is investigated in this paper. A closed-form expressions for the spurious-free dynamic range (SFDR) is obtained when a single table of offset (TO) is used in the multipartite approximation. In this case, the optimal design that minimizes storage requirement for a given SFDR can be obtained analytically. A numerical algorithm is also presented to obtain the optimal design also when two or more TOs are employed is the approximation. The VLSI implementation results and the comparison with previously proposed DDFS architectures demonstrate the effectiveness of multipartite table methods for the realization of high performance direct digital synthesizers.