ASIP array system performance analysis and design space exploration using SystemC

In this paper we present a design methodology to address the allocation/scheduling problem of a given parallel application task precedence graph (TPG) to a multiprocessor architecture referred to as ASIP array system using SystemC simulation models. The basic rationale of the proposed method is to develop modeling constructs and library in SystemC to help designers automate the process of generation of executable specification models based on a given task graph allocation decision. The main goal of this work is to rapidly evaluate different architectural alternatives in terms of time, energy and area cost. The viability and potential of the proposed methodology is demonstrated by an illustrative case study.