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A low-cost serial decoder architecture for low-density parity-check convolutional codes

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6 Author(s)
Bates, S. ; Dept. of Electr. & Comput. Eng., Alberta Univ., Edmonton, AB ; Zhengang Chen ; Gunthorpe, L. ; Pusane, A.E.
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We propose a low-cost serial decoder architecture for low-density parity-check convolutional codes (LDPC-CCs). It has been shown that LDPC-CCs can achieve comparable performance to LDPC block codes with constraint length much less than the block length. The proposed serial decoder architecture for LDPC-CCs uses a single decoding processor. Terminated data frames are sent through the processor iteratively until correctly decoded or a maximum number of iterations is reached. This architecture saves memory consumption and uses a very small number of logic elements, making it especially suitable for strong LDPC-CCs with large code memory. The proposed architecture is realized for a (2048,3,6) regular LDPC-CC on an Altera Stratix FPGA. With a maximum of 100 iterations, the design achieves up to 9-Mb/s throughput using only a very small portion of the field-programmable gate array resources.

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Circuits and Systems I: Regular Papers, IEEE Transactions on  (Volume:55 ,  Issue: 7 )