Skip to Main Content
Notice of Violation of IEEE Publication Principles
"A Dual Channel DVB-S S2 Direct-Conversion Satellite TV Tuner with On-Chip ADCs and Multiple DC Offset Cancellation Loops"
by Maxim, A.; Turinici, C.; Gheorge, M.;
in the Proceedings of the IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, 2008. SiRF 2008. 23-25 Jan. 2008 Page(s):5 - 8
After careful and considered review, it has been determined that the above paper is in violation of IEEE's Publication Principles.
Specifically, the paper describes a product that the author later admitted is not real. In response to an inquiry on this misconduct, Mr. Maxim acknowledged that the following people who have been listed as co-authors on several of his papers are fabricated names and that he is the only author:
C. Turinici, D. Smith, S. Dupue, M. Gheorge, R. Johns, D. Antrik
Additionally, in papers by Mr. Maxim that have co-authors other than those listed above, it was discovered in some cases that he had not consulted with them while writing the papers, and submitted papers without their knowledge.
Although Mr. Maxim maintains that not all of the data is falsified, IEEE nevertheless cannot assure the integrity of papers posted by him because of his repeated false statements.
Due to the nature of this violation, reasonable effort should be made to remove all past references to the above paper, and to refrain from any future references.This paper proposes a dual channel satellite TV receiver using an alternative partition into a front-end RF-todigital tuner that includes the baseband ADC converters and a digital-only demodulator-on-host, resulting in a low cost and a good isolation between the analog front-end and the digital backend. The die area was significantly reduced by replacing the multi-oscillator solution used at present with a single high frequency Colpitts oscillator, followed by a ratiometric frequency divider that generates th- local oscillator signals for the entire satellite TV L-band. VCO pulling was reduced by having a larger frequency offset between the two PLLs, while the ADC spurs were avoided by performing a dynamic clock frequency management. The DC offset cancellation loop capacitors were integrated onchip by combining a multiple loop architecture with Miller capacitance multiplication. Tuner specifications include: -85dBm sensitivity, <7dB noise figure, +26dBm IIP3 at minimum gain,<0.7?? total integrated phase noise, 24mm2 die area and 2W power from a 3.3V supply in dual channel reception mode.