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A high linearity pulsewidth control loop (PWCL) is proposed in this paper. Using the linear control stage (CS) and digital-controlled charge pump (DCCP), the proposed PWCL can be operated within a wide-range of both input and output duty cycles over a wide frequency range. A simple detection circuit is utilized to control the DCCP in a complementary architecture such that the proposed PWCL can reduce the locking time ratio to 4.5. The test chip is fabricated using 0.18 mum CMOS process. The measurement results show that the frequency range of the input signal was 1 MHz to 1.3 GHz, the duty cycle range of the input signal is from 30% to 70% and the programmable duty cycle of the output signal is from 30% to 70% in steps of 5%. The measurement power dissipation and the peak-to-peak jitter are 4.8 mW and 13.2 ps, respectively, at an operating frequency of 1.3 GHz.
Date of Publication: Feb. 2008