Referenced Items are not available for this document.
In this paper, starting from theoretical considerations on the chosen architecture, chip design and measurement results are presented for a continuous-time quadrature bandpass sigma-delta (SigmaDelta) modulator for a combined GPS and Galileo low-IF receiver. The modulator chip was designed in a standard 0.25 mum CMOS technology. The designed CT quadrature bandpass SigmaDelta modulator has a power consumption of 20.5 mW with 1.8-V supply voltage, a dynamic range of 57.5 dB and 50.2 dB and a peak SNDR of 52.9 dB and 48.4 dB for GPS/Galileo, respectively. The core area of the chip is 0.37 times 0.54 mm2.
Published in:
Radio-Frequency Integration Technology, 2007. RFIT 007. IEEE International Workshop on
Date of Conference: 9-11 Dec. 2007
- Page(s):
- 127 - 130
- E-ISBN :
- 978-1-4244-1308-9
- Print ISBN:
- 978-1-4244-1307-2
- INSPEC Accession Number:
- 9766056
- Conference Location :
- Rasa Sentosa Resort
- Digital Object Identifier :
- 10.1109/RFIT.2007.4443935
- Product Type:
- Conference Publications
About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies
A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2013 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.
