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A Simulink Model for All-Digital-Phase-Locked-Loop

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4 Author(s)
Xiaoyan Wang ; Integrated Circuits and Systems Laboratory, Institute of Microelectronics, Singapore. wangxy@ime.a-star.edu.sg ; Yeung Bun Choi ; Mingkyu Je ; Wooi Gan Yeoh

A Simulink model for all-digital-phase-locked-look (ADPLL) is proposed in this paper. The study is based on ADPLL implemented in an all-digital RF transceiver. Simulation results in Simulink give the performance overview of the ADPLL.

Published in:

Radio-Frequency Integration Technology, 2007. RFIT 007. IEEE International Workshop on

Date of Conference:

9-11 Dec. 2007