By Topic

A Fully Integrated Digital Hearing Aid Chip With Human Factors Considerations

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
Sunyoung Kim ; Korea Adv. Inst. of Sci. & Technol., Daejeon ; Seung Jin Lee ; Namjun Cho ; Seong-Jun Song
more authors

A low-power digital hearing aid chip with consideration of the human external ear characteristics according to the each individual user is proposed and implemented. It adopts the pre fitting verification algorithm (PREVA) to obtain the fast and accurate gain fitting and verification in two steps, coarse and fine gain fittings. The ear canal modeling filter circuit (EMC) which models the human external ear into the distributed LC filter enables the coarse gain fitting based on the shape of the external ear of the patient. The fine fitting verification is performed by the external inputs from the hearing loss test results. To reduce the power consumption of the human factored hearing aid chip design, the multi-threshold preamplifier, the adaptive fitting digital signal processor (DSP) with the filter reuse technique and the gated successive approximation ADC are designed and embedded to the digital hearing aid chip. The dynamic range of the multi-threshold preamplifier exists from 0.45 V to 0.8 V and dissipates 32 muW from a single 0.9 V supply. The fabricated digital hearing aid chip achieves the peak SNR of 81 dB in the overall system with 4.2 muV of input-referred noise voltage. The fabricated chip occupies the core area of 3.12times1.20 mm2 in a 0.18 mum standard CMOS technology and consumes only 107 muW from a single 0.9 V supply.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:43 ,  Issue: 1 )