Referenced Items are not available for this document.
A 34-million transistor stream processor system-on-chip (SoC) for signal, image, and video processing contains 80 parallel integer ALUs organized into 16 data-parallel lanes with a 5-ALU VLIW per lane, two CPU cores, and I/Os. Implemented in a 0.13 mum CMOS technology, sixteen 800 MHz data-parallel lanes combine to deliver performance of 512 8-bit GOPS or 256 16-bit GOPS, or 128 billion 16-bit multiply-accumulates per second GMACs), with a power efficiency of 82 pJ/MAC.
Published in:
Solid-State Circuits, IEEE Journal of
(Volume:43
,
Issue:
1
)
Date of Publication: Jan. 2008
- Page(s):
- 202 - 213
- ISSN :
- 0018-9200
- INSPEC Accession Number:
- 9757284
- Digital Object Identifier :
- 10.1109/JSSC.2007.909331
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 28 January 2008
- Issue Date :
- Jan. 2008
- Sponsored by :
- IEEE Solid-State Circuits Society
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