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Evaluation of Traffic Pattern Effect on Power Consumption in Mesh and Torus Network-on-Chips

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3 Author(s)
S. Koohi ; Sharif University of Technology, Tehran, Iran, ; M. Mirza-Aghatabar ; S. Hessabi

Technology scaling increases clock rates and die sizes; therefore, power dissipation is predicted to soon become the key limiting factor on the performance of single-chip designs. NoC as an efficient and scalable on-chip communication architecture for SoC architectures, enables integration of a large number of computational and storage blocks on a single chip. Since different applications impose different traffic models to the network, in this paper we will analyze the power and energy consumption of the most popular traffic models, i.e., uniform, local, HotSpot and first matrix transpose, in two famous and well designed topologies, mesh and torus. We will also compare these topologies with considering two figures of merit, i.e. power consumption and power per throughput ratio and choose the best topology under different traffic models with respect to each of these figures of merit.

Published in:

2007 International Symposium on Integrated Circuits

Date of Conference:

26-28 Sept. 2007