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Leakage power is found to be the dominant contributor to total power consumption at present technology level. Large amount of power can be saved if it is taken care early in the design cycle during logic synthesis. While most of the works on FSM synthesis target optimization of switching activity for minimizing dynamic power, yet inclusion of an accurate model for static (leakage) power during synthesis can lead to a considerable saving in total power consumption. In this paper a genetic algorithm based FSM synthesis technique is presented for minimizing dynamic power together with leakage power reduction both in combinational and sequential part of FSM. Simulation results show 22.18% improvement in static power and 8.02% improvement in dynamic power when compared with NOVA. A trade-off between static and dynamic power also has been done.