By Topic

Synthesis of Finite State Machines for Low Static and Dynamic Power

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Saurabh Chaudhury ; Department of E & ECE, Indian Institute of Technology Kharagpur, India, email: saurabh@ece.iitkgp.ernet.in ; Santanu Chattopadhyay ; Krishna Teja S.

Leakage power is found to be the dominant contributor to total power consumption at present technology level. Large amount of power can be saved if it is taken care early in the design cycle during logic synthesis. While most of the works on FSM synthesis target optimization of switching activity for minimizing dynamic power, yet inclusion of an accurate model for static (leakage) power during synthesis can lead to a considerable saving in total power consumption. In this paper a genetic algorithm based FSM synthesis technique is presented for minimizing dynamic power together with leakage power reduction both in combinational and sequential part of FSM. Simulation results show 22.18% improvement in static power and 8.02% improvement in dynamic power when compared with NOVA. A trade-off between static and dynamic power also has been done.

Published in:

2007 International Symposium on Integrated Circuits

Date of Conference:

26-28 Sept. 2007