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In this paper, the design of a 1.2 V charge pump circuit suitable for PLL-based frequency synthesizer with low spurious tone requirement is presented. The proposed charge pump circuit improves current matching in a wide output voltage range by applying a replica biasing technique with a new feedback structure that provides more stable operation. The systematic percentage error for the output range from 0.1 V to 1.1 V is less than plusmn0.5 %. Other non-ideal effects such as feed-through of the input pulses, charge sharing and timing mismatch of input signals are also significantly reduced. The charge pump circuit was designed in 0.18 mum CMOS process.
Date of Conference: 26-28 Sept. 2007