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We propose a simple asynchronous (async) design methodology for designing async circuits using the commercial IC design tools and standard library cells. The methodology involves using a proposed async latch controller, synthesizing the datapath circuits and state machines that linked by the latch controller, and using the standard back-end design flows for simulations, layout and verification. The methodology can serve as a simple and fast alternative in async circuit design as other async methodologies and tools are not easy obtainable (except for some institutions), or are not easy to be appreciated by designers, or both. A 32-tap 16-bit finite impulse response (FIR) filter is used to demonstrate the practicability and validity of the proposed methodology, and the async FIR filter dissipates ~ 8nJ @ 3.3V, features a delay of ~ 0.73mus @ 3.3V per complete computation, and occupies CMOS process. 0.58mn2 @ 0.35mum.