By Topic

Steady-State and Dynamic Study of Active Power Filter With Efficient FPGA-Based Control Algorithm

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Zeliang Shu ; Southwest Jiaotong Univ., Chengdu ; Yuhua Guo ; Jisan Lian

A new approach using field-programmable gate array (FPGA) to implement a fully digital control algorithm of active power filter (APF) is proposed in this paper. This FPGA-based controller integrates the whole signal-processing function of an APF, including synchronous-reference-frame transform, low-pass filter, three-phase phase-locked loop, inverter-current controller, etc. By case studies on the principle, performance, and architecture, these control blocks are implemented in real-time and synthesized into a medium-scale FPGA chip by adopting some useful digital-signal-processing techniques, such as pipelining, folding and strength reduction, with respect to minimization of hardware resource and enhancement of operating frequency. As a result, the whole algorithm needs around 5000 logic elements and can run at synchronous system-clock rates of up to 65 MHz. Experimental results on a laboratory prototype are given to demonstrate performance of the proposed approach during steady-state and dynamic operations.

Published in:

Industrial Electronics, IEEE Transactions on  (Volume:55 ,  Issue: 4 )