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Exploiting Slack Time in Dynamically Reconfigurable Processor Architectures

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6 Author(s)
Thomas Schweizer ; Department of Computer Engineering, University of Tuebingen, Sand 13, 72076 Tuebingen, Germany. crc@informatik.uni-tuebingen.de ; Tobias Oppold ; Julio Oliveira Filho ; Sven Eisenhardt
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In dynamically reconfigurable processors, different contexts as well as different data paths within one context usually vary in their execution time. Voltage scaling offers the ability to utilize this variation to reduce power consumption. In this paper, we propose a dual-VDD dynamically reconfigurable processor architecture which utilizes the varying execution time to reduce dynamic power consumption without adapting the clock frequency. Gate-level simulations reveal that the proposed dual-VDD architecture reduces the power consumption of a processing element up to 22.1% and the total power consumption up to 10.5% compared to a single voltage architecture instance.

Published in:

Field-Programmable Technology, 2007. ICFPT 2007. International Conference on

Date of Conference:

12-14 Dec. 2007