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Unifying FPGA Hardware Development

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3 Author(s)
Jacob A. Bower ; Department of Computing, Imperial College, 180 Queen's Gate, London SW7 2AZ, UK. ; Wei Ning Cho ; Wayne Luk

In current FPGA development environments complex projects often end up in an ad-hoc tangle of programming systems; examples include Perl, Makefiles, and Ver-ilog and/or VHDL. To combat this we develop an approach to FPGA development in which a single specification is used to combine: high-and low-level description of custom hardware, parameterisation of existing IP and project build. In this paper we present an abstract overview of our unified approach and a prototype implementation called YAHDL, composed of a set of libraries written in the object-oriented software language Ruby. To explore YAHDL's effectiveness we apply it to an existing project, creating FPGA hardware designs for floating-point Monte Carlo simulations. With this case-study we show it is possible to use YAHDL to simplify the generation of application specific instances of our Monte Carlo architectures while achieving performance in the 200-300 MHz range.

Published in:

Field-Programmable Technology, 2007. ICFPT 2007. International Conference on

Date of Conference:

12-14 Dec. 2007