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Asymmetric Multi-Processor Architecture for Reconfigurable System-on-Chip and Operating System Abstractions

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3 Author(s)
Xin Xie ; Univ. of Queensland Brisbane, Brisbane ; Williams, J. ; Bergmann, N.

We propose an asymmetric multi-processor reconflgurable SoC architecture comprised of a master CPU running embedded Linux and loosely-coupled slave CPUs executing dedicated software processes. The slave processes are mapped into the host OS as ghost processes, and are able to communicate with each other and the master via standard operating system communication abstractions. Custom hardware accelerators can be also added to the slave or master CPUs. We describe an architectural case study of an MP3 decoding application of 12 different single and multi-CPU configurations, with and without custom hardware. Analysis of system performance under master CPU load (computation and IO), and a time-area cost model reveals the counter-intuitive result that multiple CPUs and appropriate software partitioning can lead to more efficient and load-resilient architecture than a single CPU with custom hardware offload capabilities, at a lower design cost.

Published in:

Field-Programmable Technology, 2007. ICFPT 2007. International Conference on

Date of Conference:

12-14 Dec. 2007

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